1. Field of the Invention
The present invention relates to a semiconductor device and method for manufacturing the device. More particularly, the present invention relates to a floating gate in a non-volatile memory device having a self-aligned shallow trench isolation structure and the method of making the device.
2. Description of the Related Art
Semiconductor memory devices can in general be divided into volatile memory devices and non-volatile memory devices. Random access memory (RAM) devices and dynamic random access memory (DRAM) device are examples of volatile memory devices. Static random access memory (SRAM) device and read only memory (ROM) devices are examples of non-volatile memory devices. In volatile memory, the stored data on the cell is destroyed if the power is interrupted while in non-volatile memory the stored data on the cell is retained even when the power is temporarily interrupted.
Among those ROM devices, there is an increased demand for flash memory devices or electrically erasable and programmable ROM (EEPROM) devices capable of inputting and outputting data electrically. A flash memory device is a kind of advanced EEPROM, in which the input and output of data are electrically controlled by F-N (Fowler-Nordheim) tunneling or a channel hot electron injection.
Highly integrated flash memory can be used as a storage media similar to a magnetic disk because it has advantages over traditional ROM devices such as a small cell area, a fast access time, low power dissipation, etc. However, for flash memory devices to replace magnetic disk memory, the cost per bit must be reduced. Decrease in the cost per bit may, in general, be accomplished by decreasing the number of manufacturing processes and the cell size.
FIG. 1 is a cross-sectional view illustrating a conventional method of manufacturing a flash memory device having a self-aligned shallow trench isolation structure.
Referring to FIG. 1, an oxide layer, a first polycrystalline silicon layer, and a nitride layer are successively formed on a silicon substrate 10 and then, these layers are patterned by a photolithography process to form a tunnel oxide layer 12, a first floating gate 14, and a nitride layer pattern 16. Next, an exposed portion of the substrate 10 is etched to a predetermined depth, thereby forming a trench 18. That is, active regions and floating gates are simultaneously defined during the trench formation process using the single mask.
Thereafter, exposed portions of the trench 18 are subjected to thermal treatment in an oxygen atmosphere for curing silicon damages caused by high-energy ion bombardment during the trench etching process. By doing so, a trench inner-wall oxide layer 20 is formed along the inner surface including the bottom surface and sidewall of the trench 18 by an oxidation reaction between the exposed silicon and the oxidant.
FIG. 2 is an enlarged view showing portion “A” in FIG. 1.
During the above oxidizing process, the oxidant encroaches upon the side of the tunnel oxide layer 12 at the lower portion of the first floating gate 14 to form “bird's beaks” at both ends of the tunnel oxide layer 12 (referred to as “3” in FIG. 2). Because the bottom edge portions of the first floating gate 14 are bent outward while both end portions of the tunnel oxide layer 12 expand due to the “bird's beaks”, the lower portions of the sidewalls of the first floating gate 14 have a positive slope (referred to as “5” in FIG. 2) and a channel width (W) decreases. Here, positive slope denotes that the sidewall slope allows the sidewall to erode due to the etchant. In other words, as shown in FIG. 2, the intrusion of the oxidant into the portion underlying the nitride layer pattern 16 is blocked by the existence of the nitride layer pattern 16 to provide the negative slope at the upper portion of the sidewall of the first floating gate 14. Meanwhile, the bottom edge portion of the lower portion of the first floating gate 14 is bent outward and has a positive slope, which is eroded by the etchant introduced from the upper portion of the substrate. It is applied in the same manner as in the sidewall of a mesa structure and acts as a stopping layer for the underlying layer when the etchant is applied.
Next, a CVD-oxide layer is deposited to fill the trench 18 and is then removed by a chemical mechanical polishing (CMP) process until the upper surface of the nitride layer pattern 16 is exposed, thereby forming a field oxide layer (not shown) in the trench 18.
After removing the nitride layer pattern 16 by a phosphoric acid stripping process, a material identical to that of the first floating gate 14 is deposited to form a second polycrystalline layer for the purpose of forming a second floating gate on the upper portion of the first floating gate 14 and the field oxide layer. The second polycrystalline layer is partially removed via a photolithography process to form the second floating gate (not shown) in a cell that is separated from those of neighboring cells. The second floating gate makes electrical contact with the first floating gate 14 and functions to increase the area of a dielectric layer which is formed in a subsequent process.
In the conventional method, the channel width decreases and a void can occur in the field oxide layer because the lower portions of the sidewalls of the first floating gate 14 have the positive slope.